A shift register circuit has been of widespread applications in electronic devices such as a liquid crystal display (LCD), an electroluminescence display, or an organic light emitting diode display, and so on.
FIG. 9 shows a conventional bidirectional shift register as disclosed by U.S. Pub. No. 2009/0122951 to Tobita. The shift register SRk has three circuits with each having a function as a shift register at one stage, i.e., a gate line drive unit 41, a forward shift unit 42, and a backward shift unite 43. The gate line driver 41 is provided with an inverter having the node N1 as its input end. The inverter is composed of a capacitive element C2 and a transistor Q6 and it is a capacitive load type inverter in which the capacitive element C2 is a load element. It is noted that this inverter differs from a normal inverter in that the clock signal to be inputted to the first clock terminal CK1 is supplied as a power supply. That is, the transistor Q1 is a transistor to supply the clock signal inputted to the first clock terminal CK1 to the output terminal OUT.
Although the forward shift unit 42 itself does not include the inverter in this embodiment, the output of the inverter composed of the capacitive element C2 and the transistor Q6 of the gate line drive unit 41 is shared by the forward shift unit 42. That is, the transistor Q2An is connected to the node N2 serving as the output end of the inverter in the gate line drive unit 41. In addition, the gate of a transistor Q5n connected between the node N1n and the first power supply terminal S1 is connected to the node N2. The gate of the transistor Q2Bn is connected to the second clock terminal CK2.
Meanwhile, transistors Q1r, Q2Ar and Q2Br are connected to the backward output terminal OUTr of the backward shift unit 43. The transistor Q1r is connected between the backward output terminal OUTr and the first backward clock terminal CK1r. That is, the transistor Q1r is a transistor to supply the clock signal inputted to the first backward clock terminal CK1r to the backward output terminal OUTr. Both transistors Q2Ar and Q2Br are connected between the backward output terminal OUTr and the first power supply terminal S1. Thus, transistors Q2Ar and Q2Br function to discharge the backward output terminal OUTr. Here, the gate node of the transistor Q1r is defined as “node N1r”. 
A capacitive element C1r is provided between the gate and the source of the transistor Q1r, that is, between the node N1r and the backward output terminal OUTr. The capacitive element C1r enhances the boosting effect of the node N1r so as to correspond to the level rise of the backward output terminal OUTr. When the capacity between the gate and the channel of the transistor Q1r is sufficiently high, the capacitive element C1r may be also replaced by it and omitted.
Although the backward shift unit 43 also does not include the inverter, the output of the inverter of the gate line drive unit 41 is shared by the backward shift unit 43. That is, the transistor Q2Ar is connected to the node N2 serving as the output end of the inverter in the gate line drive unit 41. The gate of a transistor Q5r connected between the node N1r and the first power supply terminal S1 is also connected to the node N2. The gate of the transistor Q2Br is connected to the second clock terminal CK2.
FIG. 10 shows a conventional bidirectional unite shift register as disclosed by U.S. Pat. No. 7,436,923 to Tobita. In the bidirectional unit shift register, an output stage of the unit shift register SR is constituted by a transistor Q1 connected between the output terminal OUT and the first clock terminal CK1; and transistors Q2 and Q8 both connected between the output terminal OUT and the first power supply terminal S1. In other words, the transistor Q1 is a transistor that supplies a clock signal inputted to the first clock terminal CK1 to the output terminal OUT, and the transistors Q2 and Q8 are transistors that supply a potential at the first Power supply terminal S1 to the output terminal OUT thereby to discharge the output terminal OUT.
The first voltage signal Vn and the second voltage signal Vr are complementary to each other in such a manner that their levels are switched according to the direction of shift of the signals. Specifically, the first voltage signal Vn becomes HIGH level and the second voltage signal Vr becomes LOW level for a forward shift, while the second voltage signal Vr becomes HIGH level and the first voltage signal becomes LOW level for a backward shift.
The node N1 is connected to first and second pull-down circuits 41 and 42 that discharge the node N1. These first and second pull-down circuits 41 and 42 operate in such a manner that they discharge the node N1 during the non-selected period of the unit shift register SR (during the period when the node N1 is not charged), and that they do not discharge the node N1 during the period (selected period) when the unit shift register SR is selected (during the period when the node N1 is charged).
The first pull-down circuit 41 includes transistors Q5A and Q7A and a capacitive element C2A, and similarly, the second pull-down circuit 42 includes transistors Q5B and Q7B and a capacitive element C2B.
In the first pull-down circuit 41, the transistor Q5A is connected between the node N1 and the first power supply terminal S1. Herein, a node connected to the gate of the transistor Q5A is defined as a “node N3.” The transistor Q7A is connected between this node N3 and the first power supply terminal S1 so that its gate is connected to the node N1. The capacitive element C2A is connected between the node N3 and the first clock terminal CK1.
The capacitive element C2A and the transistor Q7A form an inverter using the node N1 as the input end and the node N3 as the output end. That is, this inverter is an inverter with capacitive load, using the capacitive element C2A as its load element, and its output is inputted to the gate of the aforementioned transistor Q5A. However, this inverter differs from traditional ones in that its power supply is a clock signal inputted to the first clock terminal CK1. That is, this inverter operates in an alternating manner by being activated by a clock signal inputted to the first clock terminal CK1. Thus, the capacitive element C2A serves not only as the load element of the inverter but also as a coupling capacitance between the output end of the inverter and the first clock terminal CK1.
The second pull-down circuit 42 has a similar configuration to the aforementioned first pull-down circuit 41. The transistor Q5B is connected between the node N1 and the first power supply terminal S1. Herein, a node connected to the gate of the transistor Q5B is defined as a “node N4.” The transistor Q7B is connected between the node N4 and the first power supply terminal S1 so that its gate is connected to the node N1. The capacitive element C2B is connected between the node N4 and the second clock terminal CK2.
The capacitive element C2B and the transistor Q7B form an inverter using the node N1 as the input end and the node N4 as the output end. In other words, this inverter is an inverter with capacitive load, using the capacitive element C2B as its load element, and its output is inputted to the gate of the aforementioned transistor Q5B. However, this inverter differs from traditional ones in that its power supply is a clock signal inputted to the second clock terminal CK2. That is, this inverter operates in an alternating manner by being activated by a clock signal inputted to the second clock terminal CK2. Thus, the capacitive element C2B serves not only as the load element of the inverter but also as a coupling capacitance between the output end of the inverter and the second clock terminal CK2.
However, such conventional bidirectional unite shift registers may cause large power consumption due to following reasons. Firstly, both of the two bidirectional unite shift registers include an inverter structure or the like which may result in larger power consumption. Secondly, as the gate of the transistors Q1 is connected to the first clock terminal CK1 for receiving the clock signal inputted and the drain of the transistors Q1 is connected to the output terminal OUT for outputting signals, the output terminal will be vulnerable to clock coupling effect, which may result in larger power consumption and unstable outputting wave form.
Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.